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IBM0418A86LQKA IBM0436A86LQKA IBM0418A86SQKA IBM0436A86SQKA 8 Mb Synchronous Communication SRAM
Features
* 100% bus utilization at high frequencies * Optimized control logic for minimum control signal interface * CKE to enable or suspend clock operations * Three chip enable pins (CE, CE2, CE2) for depth expansion with double cycle deselect * Single Read/Write control pin (R/W) * Individual Byte Write controls * Synchronous Pipeline Mode of Operation with fully coherent Self-Timed Late-Late-Write * Sleep mode, for reduced stand-by power * 100-pin TQFP package * 3.3 V (SQKA) or 2.5 V (LQKA) power supply and I/O * LVTTL input and output levels * 256K x 36 or 512K x 18 organization * Registered control inputs, addresses and data I/O * Burst feature supports interleaved or linear burst orders
Description
The IBM0418A86LQKA/SQKA and IBM0436A8LQKA/SQKA are 8 Mb Synchronous Pipeline SRAMs specifically optimized for communication system applications. These SRAMs utilize the Late-Late-Write protocol and optimized I/O timing parameters to permit 100% bus utilization for any sequence of read and write operations. Please consult application notes for an example at: http://www.chips.ibm.com/techlib/products/commun/appnotes.html. Developers of non-network system communication applications should contact their local IBM representative for a suitability assessment and SRAM recommendation. The clock input (CLK) is used to register all synchronous input pins on its rising edge. Synchronous inputs include clock enable (CKE), chip enable (CE, CE2 and CE2), cycle start input (ADV/LD), all addresses (SA), read/write control (R/W), byte write controls (BWa, BWb, BWc, BWd) and all data inputs (DQ). Asynchronous inputs include output enable (OE), which may be carefully timed to optimally reduce bus turn-around time, and Sleep enable (ZZ). The static burst mode pin (MODE) selects between interleaved and linear burst modes and should be tied high (or left unconnected) for interleaved burst order (or if Burst Mode is not used), or tied low for linear burst order. Read, Write and Deselect cycles (see Read/Write Command Truth Table on page 7) are initiated with ADV/LD = low. Subsequent Read or Write operations can load new addresses (ADV/LD = low), or use the internally generated burst address if ADV/LD = high (See Burst Sequence Truth Tables on page 7) based on the initial address that was loaded. For write operations, Byte Write inputs (BWa, BWb, BWc, BWd) are registered each cycle the address is loaded externally, or advanced from the i burst counter, data is registered two active cycles later. Sleep mode is enabled by switching asynchronous signal ZZ High. When the SRAM is in Sleep mode, the outputs will go to a High-Z state, and the SRAM will draw a standby current of ISB2Z after a delay of tZZI. SRAM data will be preserved during Sleep mode, but any read or write operation that is pending while entering Sleep mode is not guaranteed. A recovery time (tZZR) is required before the SRAM resumes normal operation. The SRAM operates from a single 3.3 V or 2.5 V power supply, and supports LVTTL I/O levels.
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Page 1 of 16
IBM0418A86LQKA IBM0436A86LQKA IBM0418A86SQKA IBM0436A86SQKA 8 Mb Synchronous Communication SRAM
Pinout
(Top View)
SA NC NC VDDQ VSS NC DQa DQa DQa VSS VDDQ DQa DQa VSS VDD VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 81 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 100 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 3031 1
SA SA SA NC/SA* ADV/LD OE (G) CKE R/W CLK VSS VDD CE2 BWa BWb NC NC CE2 CE SA SA
x18
SA SA SA SA SA SA SA DNU DNU VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE (LBO)
SA SA SA NC/SA* ADVLD OE (G) CKE R/W CLK VSS VDD CE2 BWa BWb BWc BWd CE2 CE SA SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 50 82 49 83 48 84 47 85 46 86 45 87 44 88 43 89 42 90 41 81 40 92 39 93 38 94 37 95 36 96 35 97 34 98 33 99 32 100 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1
NC/DQb** NC NC DQb NC DQb VDDQ VDDQ VSS VSS NC DQb NC DQb DQb DQb DQb DQb VSS VSS VDDQ VDDQ DQb DQb DQb DQb VDD VSS VDD VDD VDD VDD VSS ZZ DQb DQa DQb DQa VDDQ VDDQ VSS VSS DQb DQa DQb DQa DQb DQa NC DQa VSS VSS VDDQ VDDQ NC DQa NC DQa NC/DQa** NC
x36
SA SA SA SA SA SA SA DNU DNU VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE (LBO)
NC/DQc** DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc VDD VDD VDD VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd NC/DQd**
* Pin 84 is reserved for address expansion. ** NC for x32, DQx for x36.
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llwp.03 10/11/2000
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IBM0418A86LQKA IBM0436A86LQKA IBM0418A86SQKA IBM0436A86SQKA 8 Mb Synchronous Communication SRAM
Ordering Information
Part Number IBM0418A86LQKA-6 IBM0418A86LQKA-7 2.5/2.5 IBM0418A86LQKA-7F IBM0418A86LQKA-10 512K x 18 IBM0418A86SQKA-6 IBM0418A86SQKA-7 3.3/3.3 IBM0418A86SQKA-7F IBM0418A86SQKA-10 IBM0436A86LQKA-6 IBM0436A86LQKA-7 2.5/2.5 IBM0436A86LQKA-7F IBM0436A86LQKA-10 256K x 36 IBM0436A86SQKA-6 IBM0436A86SQKA-7 3.3/3.3 IBM0436A86SQKA-7F IBM0436A86SQKA-10 7.5/4.2 10.0/5.0 LVTTL Pipeline 6.0/3.5 6.7/3.8 7.5/4.2 10.0/5.0 7.5/4.2 10.0/5.0 6.0/3.5 6.7/3.8 LVTTL Pipeline 6.0/3.5 6.7/3.8 7.5/4.2 10.0/5.0 Organization Function VDD /VDDQ (Volts) Cycle/Access (ns) 6.0/3.5 6.7/3.8
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IBM0418A86LQKA IBM0436A86LQKA IBM0418A86SQKA IBM0436A86SQKA 8 Mb Synchronous Communication SRAM
Pin Descriptions
Symbol CLK Type Input Description Clock: This signal registers the address, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around clock's rising edge. Synchronous Clock Enable: This active low input enables the CLK input. When high, the CLK input is ignored, and the previous cycle is extended. Synchronous Chip enable: These active low inputs are used to enable the device and are sampled only when a new external address is loaded (ADV/LD low). Double cycle deselect protocol. Synchronous Chip enable: This active high input is used to enable the device and is sampled only when a new external address is loaded (ADV/LD low). Double cycle deselect protocol. Synchronous Address Advance/Load: When low, a new address is loaded into the device (and Burst counter). When high, the internal burst counter is advanced and used (R/W is ignored). Synchronous Address Inputs. SA0 and SA1 are the least significant Address bits, and are used to set the Burst Address counter for Burst operations. Pin 84 is reserved as the High order Address for the 16 Mb Late-Late-Write SRAM. Synchronous Byte Writes: These inputs allow individual bytes to be written (low), or masked (high) during a write operation. Byte writes are registered on the same clock edge as the Write Address (whether it is an externally provided or internally generated Address). These inputs have no effect during a Read operation. Read/Write: This synchronous input, sampled at the rising edge of CLK when ADV/LD is low, determines whether a Read (high) or Write (low) operation is initiated. For Write operations, the Byte Write Enable inputs provide byte control for Partial Write operations. Output Enable: This active low, asynchronous input enables the Output Drivers. Mode: A low on this pin selects Linear Burst order. A high or NC will default to Interleaved Burst order. Do not change input state once the device is operating.
CKE CE CE2 CE2
Input
Input
Input
ADV/LD SA0 SA1 SA BWa BWb BWc
Input
Input
Input
R/W
Input
OE MODE(LBO) DQa DQb DQc DQd
Input Input
Input/Output
Data I/Os: DQa is Data Input and Output for Byte "a". DQb is for Byte "b",DQc is for Byte "c" and DQd is for Byte "d".
ZZ
Input
Sleep Enable: This active high, asynchronous input causes the chip to enter Sleep Mode, which is a low standby-current state. While ZZ is high, all other inputs are ignored, and data in the memory array is retained. Pin may be left unconnected. No Connect: These pins can be left unconnected, or may be connected to GND to minimize thermal impedance or any other DC input. Power Supply: See DC Electrical Characteristics on page 9 and Recommended DC Operating Conditions on page 8 for range. Isolated Output Buffer Supply: See DC Electrical Characteristics on page 9 and Recommended DC Operating Conditions on page 8 for range. Ground: GND. Do Not Use. Reserved pins. These can either be left unconnected or wired to GND to improve thermal impedance.
NC VDD VDDQ VSS DNU
NC
Supply
Supply Supply NC/Input
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IBM0418A86LQKA IBM0436A86LQKA IBM0418A86SQKA IBM0436A86SQKA 8 Mb Synchronous Communication SRAM
SRAM Features
Late-Late-Write In the Late-Late-Write QBT (Quick Bus Turn) function, write data must be registered on the N+2 clock cycle and addresses and controls registered on the N base clock cycle. Read data is available in the N+1 clock cycle. Read data is valid for a full cycle plus access time from the time the address is registered. Write data must be provided with set-up time two cycles after the valid address. This provides 100% bus utilization. In the unique case when a read cycle occurs after a write cycle to the same address, write data information is stored temporarily in holding registers. During the first write cycle preceded by a read cycle, the SRAM array will be updated with the address and data from the holding registers. Read cycle addresses are monitored to determine if read data is supplied from the SRAM array or from the write buffer holding registers. Bypassing the SRAM array occurs on a byte-by-byte basis. When only one byte is written during a write cycle, read data from the address last written will have new byte data from the write buffer and the remaining bytes from the SRAM array. Late-Late-Write is extremely similar to Late-Write; just one additional cycle is needed to register the write data. Burst Mode The IBM0418/36A86 SRAM can operate in either linear or interleave burst modes using the LBO pin. Addresses are loaded via the ADV/LD pin. Once an address is loaded, it is designated as either a write or read address from the initial address load. All burst addresses produced by ADV pulses are either read or write as designated by the initial address. Only read OR write operation within a burst-loaded address is supported. Power Down Mode Power Down Mode, or "Sleep Mode," is accomplished by switching asynchronous signal ZZ high. When powering-down the SRAM inputs must be dropped first and VDDQ must be dropped before or simultaneously with VDD. Power-Up Requirements In order to guarantee the optimum internally regulated supply voltage, the SRAM requires 50 s of power-up time after VDD reaches its operating range. SRAM power-up requires VDD to be powered before or simultaneously with VDDQ and inputs after VDDQ. VDDQ should not exceed VDD supply by more than 0.4 V during power-up. Sleep Mode Operation Sleep mode is a low-power mode initiated by bringing the asynchronous ZZ pin high. During Sleep mode, all other inputs are ignored and outputs are brought to a High-Z state. Sleep mode current and output High-Z are guaranteed after the specified Sleep mode enable time. During Sleep mode, the array data contents are preserved. Sleep mode must not be initiated until after all pending operations have completed, as any pending operation is not guaranteed to properly complete after Sleep mode is initiated. Sense amp data is lost. Normal operation can be resumed by bringing ZZ low, but only after specified Sleep mode recovery time.
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IBM0418A86LQKA IBM0436A86LQKA IBM0418A86SQKA IBM0436A86SQKA 8 Mb Synchronous Communication SRAM
Cycle Definition Truth Table
Operation Deselect Cycle Deselect Cycle Deselect Cycle Deselect Cycle (Continue) Read Cycle (Begin Burst) Read Cycle (Continue Burst) No Op /Dummy Read (Begin Burst) Dummy Read (Continue Burst) Write Cycle (Begin Burst) Write Cycle (Continue Burst) No Op /Write Abort (Begin Burst) Write Abort (Continue Burst) Clock Disabled (Stall) Sleep Mode Address used None None None None CE H X X X CE2 X H X X CE2 X X L X ZZ L L L L ADV/ LD L L L H R/W X X X X BWx X X X X OE X X X X CKE L L L L CLK LH LH LH LH DQ High-Z High-Z High-Z High-Z 1 Notes
External
L
L
H
L
L
H
X
L
L
LH
Q
Next
X
X
X
L
H
X
X
L
L
LH
Q
1, 2
External
L
L
H
L
L
H
X
H
L
LH
High-Z
3
Next
X
X
X
L
H
X
X
H
L
LH
High-Z
1, 2, 3
External
L
L
H
L
L
L
L
X
L
LH
D
4
Next
X
X
X
L
H
X
L
X
L
LH
D
1, 2, 4
None
L
L
H
L
L
L
H
X
L
LH
High-Z
3, 4
Next
X
X
X
L
H
X
H
X
L
LH
High-Z
1, 2, 3, 4
Current None
X X
X X
X X
L H
X X
X X
X X
X X
H X
LH X
Held High-Z
5
1. Continue Burst Cycles are initiated with the ADV/LD pin held high. The type of cycle that is performed (Deselect, Read or Write) is determined by the initial Deselect or Begin Read/Write burst cycle. 2. The address counter is incremented for all Continue Burst cycles (see Interleaved Burst Sequence Truth Table on page 7 and Linear Burst Sequence Truth Table on page 7 for Burst order and wrap information). 3. Dummy Read and Write Abort cycles can be considered Non-Operations or "NOP." All BWx inputs must be High to prevent a Write operation from being performed. 4. OE may be tied low to reduce the number of control pins for the SRAM. The device will automatically tri-state the output drivers during a Write cycle. By carefully controlling the OE timings, cycle time improvements can be obtained. 5. If a Clock Disable (CKE = High) command is issued during a Read operation, the DQ bus will remain active (Low-Z). If it occurs during a Write operation, the bus will remain inactive (High-Z), and any pending Data-In is delayed by an additional cycle. No operation will be performed during the Clock Disable cycle. * X=Don't Care, H=Logic High, L= Logic Low. BWx=H means all byte write inputs (BWa, BWb, BWc, BWd) are High. BWx=L means one or more byte write signals are Low. (See Read/Write Command Truth Table on page 7 for more information on byte enable control). * All inputs except OE and ZZ must meet setup and hold times around the rising edge of CLK * CKE held High will insert wait states. Internal device registers will hold their previous values. * On-chip circuitry is included to ensure that outputs are held in High-Z during power-up.
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llwp.03 10/11/2000
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IBM0418A86LQKA IBM0436A86LQKA IBM0418A86SQKA IBM0436A86SQKA 8 Mb Synchronous Communication SRAM
Interleaved Burst Sequence Truth Table
First Address (External) X...X00 X...X01 X...X10 X...X11 Second Address (Internal) X...X01 X...X00 X...X11 X...X10
(Mode=High or NC)
Third Address (Internal) X...X10 X...X11 X...X00 X...X01 Fourth Address (Internal) X...X11 X...X10 X...X01 X...X00
Linear Burst Sequence Truth Table
First Address (External) X...X00 X...X01 X...X10 X...X11 X...X01 X...X10 X...X11 X...X00
(Mode=Low)
Third Address (Internal) X...X10 X...X11 X...X00 X...X01 Fourth Address (Internal) X...X11 X...X00 X...X01 X...X10
Second Address (Internal)
Read/Write Command Truth Table
Function Read Abort Write (No Operation) Write Byte "a" Write Byte "b" Write Byte "c" Write Byte "d" R/W H L L L L L BWa X H L H H H BWb X H H L H H BWc X H H H L H BWd X H H H H L
1. Any combination of BWx inputs may be used during Write operations to perform partial Byte Writes. 2. Shaded area of table does not apply to the x18 part, as only BWa and BWb are provided.
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IBM0418A86LQKA IBM0436A86LQKA IBM0418A86SQKA IBM0436A86SQKA 8 Mb Synchronous Communication SRAM
Absolute Maximum Ratings
Parameter Power Supply Voltage Output Power Supply Voltage Input Voltage DQ Input Voltage Junction Temperature Operating Temperature Storage Temperature Short Circuit Output Current Symbol V DD VDDQ VIN V DQIN TJ TA TSTG IOUT Rating -0.5 to 4.3 -0.5 to VDD -0.5 to VDD +0.5 -0.5 to VDDQ+0.5 150 0 to 70 -55 to +150 25 Units V V V V Notes 1 1 1, 2 1 1 1 1 1
C C C
mA
1. Stresses greater than those listed under Absolute Maximum Ratings table may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Excludes DQ inputs.
Recommended DC Operating Conditions (TA=0 to +70 C)
Parameter Supply Voltage Symbol 2.5 V VDD 3.3 V 2.5 V Output Driver Supply Voltage V DDQ 3.3 V 2.5 V Input High Voltage VIH 3.3 V Input Low Voltage Input Leakage Current Output High Voltage (IOH =-4.0mA) VIL ILI 2.5 V VOH 3.3 V 2.5 V Output Low Voltage (IOL=8.0mA) Output Leakage Current VOL 3.3 V ILO -- -4.0 0.4 4.0 2.4 -- 0.2 V 1, 4 2.0 -0.3 -2.0 2.0 V 1, 4 -- -- VDDQ + 0.3 0.8 2.0 V 1, 3 5 3.135 1.7 3.3 -- V DD VDDQ + 0.3 V 1, 2 3.0 2.25 3.3 2.5 3.63 V DD V 1 Min. 2.25 Typ. 2.5 Max. 2.75 V 1 Units Notes
A
A
1. All voltages referenced to V SS. All VDD , VDDQ and VSS pins must be connected. VDDQ and VDD = 2.5 V or 3.3 V nominal. Mixed voltage levels for V DDQ and VDD not supported. 2. V IH(Max)DC = V DDQ + 0.3 V, VIH (Max)AC = VDDQ + 0.85 V (pulse width 4.0ns). 3. VIL(Min)DC = - 0.3 V, VIL(Min)AC= -1.5 V (pulse width 4.0ns) 4. Driver AC characteristics are higher than the shown DC values. See AC Test Loading on page 10 for actual test conditions. 5. MODE pin has an internal pull-up, and ILI = +/-100A.
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llwp.03 10/11/2000
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IBM0418A86LQKA IBM0436A86LQKA IBM0418A86SQKA IBM0436A86SQKA 8 Mb Synchronous Communication SRAM
DC Electrical Characteristics (TA=0 to +70 C, VDD=3.3 V 10% or 2.5 V 10%)
Max. Parameter Average Power Supply Current - Operating Device Selected; V IL all inputs VIH ; Cycle time tKHKH (min); VDD =max.; Outputs open Average Power Supply Current - Idle Device Selected; V SS + 0.2 all inputs VDD - 0.2; CKE V DD - 0.2; Cycle time tKHKH (min); V DD=max CMOS Standby Current Device De-selected; V SS + 0.2 all inputs VDD - 0.2; All inputs static; Clocks idle; VDD =max TTL Standby Current Device Deselected; V IL all inputs VIH ; All inputs static; Clock frequency = 0; V DD=max Clock Running Current Device Deselected; V SS + 0.2 all inputs VDD - 0.2; Cycle time tKHKH (min); V DD=max Sleep Mode Current ZZ VIH; VDD =max ISB2Z 20 20 20 20 mA Symbol -6 -7 -7F -10 Units Notes
IDD
230
210
190
140
mA
1, 2
IDD1
25
25
25
25
mA
1, 2
ISB2
25
25
25
25
mA
2
ISB3
25
25
25
25
mA
2
ISB4
85
75
65
50
mA
2
1. IDD does not include IDDQ (output driver supply) current. Current increases with faster cycle times. IDDQ is a function of Clock Frequency and output load. 2. See Cycle Definition Truth Table on page 6 for complete definition of Selected and Deselected cycles.
TQFP Thermal Characteristics
Item Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Symbol RJA RJC Rating 32 4 Units
C/W C/W
Capacitance
(TA=0 to +70 C, VDD= 3.3 V 10%, f=1 MHz)
Parameter Symbol CIN COUT Test Condition VIN = 0V VOUT = 0V Max 4 5 Units pF pF Notes 1 1
Control and Address Input Capacitance Data I/O Capacitance (DQ0-DQ35) 1. Capacitance Values are sampled.
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IBM0418A86LQKA IBM0436A86LQKA IBM0418A86SQKA IBM0436A86SQKA 8 Mb Synchronous Communication SRAM
AC Test Conditions
Parameter Output Driver Supply Voltage
(TA=0 to +70 C, VDD &VDDQ=3.3 V or 2.5 V 10%, See AC Test Loading figure below.)
Symbol VDDQ 3.3 V 2.5 V 3.3 2.0 V 3.3 V 1.5 VSS 2.5 V 1.25 V 3.3 V 2.5 V 1.5 1.25 V 3.3 V 1.5 0.5 0.5 ns ns TR TF V VDD /VDDQ 10% 2.5 V Conditions 2.5 V Units
Input High Level Input Low Level Input Timing Reference Voltage
V IH VIL
Output Reference Voltage Input Rise Time Input Fall Time
AC Test Loading
50 DQ 50 1.5 for 3.3 V 1.25 for 2.5 V 10pF
1.5 for 3.3 V 1.25 for 2.5 V
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Page 10 of 16
IBM0418A86LQKA IBM0436A86LQKA IBM0418A86SQKA IBM0436A86SQKA 8 Mb Synchronous Communication SRAM
AC Characteristics (TA = 0 to +70 C, VDD & VDDQ = 2.5 or 3.3 V)
-6 Parameter Cycle Time Clock High Pulse Width Clock Clock Low Pulse Width Clock Enable Set-up time Clock Enable Hold time Clock to Output Valid Clock to Output Invalid Clock High to Output Low-Z Output Times Clock High to Output High-Z Output Enable to Output Valid Output Enable to Low-Z Output Enable to High-Z Address Setup Time Setup Times Sync Select Setup Time Write Enables Setup Time Data In Setup Time Address Hold Time Hold Times Sync Select Hold Time Write Enables Hold Time Data In Hold Time ZZ active to input ignored ZZ inactive to input sampled ZZ active to Sleep current ZZ inactive to exit Sleep current Symbol Min tKHKH tKHKL tKLKH tEVKH tKHEX tKHQV tKHQX tKHQX1 tKHQZ tGLQV tGLQX tGHQZ tAVKH tCVKH tWVKH tDVKH tKHAX tKHCX tKHWX tKHDX tZZ tRZZ tZZI tRZZI 6.0 2.0 2.0 1.5 0.5 -- 1.5 1.5 1.5 -- 0.0 -- 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.0 0.0 Max -- -- -- -- -- 3.5 -- -- 3.0 3.5 -- 3.0 -- -- -- -- -- -- -- -- 2(tKHKH) 2(tKHKH) 2(tKHKH) -- Min 6.7 2.2 2.2 1.5 0.5 -- 1.5 1.5 1.5 -- 0.0 -- 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.0 0.0 Max -- -- -- -- -- 3.8 -- -- 3.0 3.8 -- 3.0 -- -- -- -- -- -- -- -- 2(tKHKH) 2(tKHKH) 2(tKHKH) -- Min 7.5 2.5 2.5 1.5 0.5 -- 1.5 1.5 1.5 -- 0.0 -- 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.0 0.0 Max -- -- -- -- -- 4.2 -- -- 3.5 4.2 -- 3.5 -- -- -- -- -- -- -- -- 2(tKHKH ) 2(tKHKH ) 2(tKHKH ) -- Min 10 3.0 3.0 1.5 0.5 -- 1.5 1.5 1.5 -- 0.0 -- 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.0 0.0 Max -- -- -- -- -- 5.0 -- -- 3.5 5.0 -- 4.0 -- -- -- -- -- -- -- -- 2(tKHKH) 2(tKHKH) 2(tKHKH) -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1, 2 1, 2 1 1, 2 1, 2 -7 -7F -10 Units Notes
Sleep Mode
0.0
0.0
0.0
0.0
ns
0.0
0.0
0.0
0.0
ns
1. AC Test Loading on page 10. 2. This parameter is sampled. Transition is measured 200mV from steady-state.
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Page 11 of 16
IBM0418A86LQKA IBM0436A86LQKA IBM0418A86SQKA IBM0436A86SQKA 8 Mb Synchronous Communication SRAM
NOP, Stall, and Deselect Cycles
T0 CLK CKE CE ADV, LD RW BWn ADDRESS
A1 A2 A3 A4 A5
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
DQ
D(A1)
Q(A2)
Q(A3)
D(A4)
Q(A5)
Command
Write D(A1)
Read Q(A2)
Clock Stall
Read Q(A3)
Write Q(A4)
Clock Stall
NOP Dummy Write
Read Deselect Continue Deselect Q(A5)
Q(A3) data extended from CKE High
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Page 12 of 16
IBM0418A86LQKA IBM0436A86LQKA IBM0418A86SQKA IBM0436A86SQKA 8 Mb Synchronous Communication SRAM
Read Write Cycles
T0 T1 T2 tKHKH CLK tEVKH tKHEX CKE tCVKH tKHCX CE ADV, LD RW BWn ADDRESS
A0 A1 A2 A3 A4 A5 A6 A7
T3 tKLKH
T4
T5
T6
T7
T8
T9
T10
tKHKL
tAVKH tKHAX
tDVKH tKHDX
tKHQX1 tKHQV tKHQX
tKHQZ tKHQX
Q(A4)+1 D(A5) Q(A6)
tKHQZ
D(A7)
DQ
Q(A0)
Q(A1)
D(A2)
D(A2)+1
Q(A3)
Q(A4)
tGLQV tGLQX OE Command Read Q(A0) Read Q(A1) Write D(A2) Burst Write D(A2+1) Read Q(A3) Read Q(A4) Burst Read Q(A4+1) Write D(A5) Read Q(A6) Write D(A7) Deselect tGHQZ
Q(A1) data is gated by asynchronous OE. Read data can always be gated by OE; even burst generated addresses data.
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IBM0418A86LQKA IBM0436A86LQKA IBM0418A86SQKA IBM0436A86SQKA 8 Mb Synchronous Communication SRAM
Sleep Mode
T0 T1 T2 tZZ CLK tZZI ZZ ISUPPLY All inputs except ZZ DQ IISB2Z Read or Deselect Only tRZZI T3 T4 T5 T6 T7 tRZZ T8
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IBM0418A86LQKA IBM0436A86LQKA IBM0418A86SQKA IBM0436A86SQKA 8 Mb Synchronous Communication SRAM
100-Pin TQFP Package Diagram
Pin 1 I.D.
22.00 0.20 20.00 0.10
14.00 0.10 16.00 0.20 1.40 0.10 12 Typ 1.60 Max
0.05/0.15 (Min/Max) 12 Typ
0.30 0.05
0.65 Basic
1.60 MAX 6 4 0.25 Seating Plane 0.10 Max Standoff 0.05/0.15(Min/Max) Lead Coplanarity Rad 0.20 Typ 0.60 + 0.15/-0.10 Note: All dimensions in Millimeters
0- 7
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(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
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IBM0418A86LQKA IBM0436A86LQKA IBM0418A86SQKA IBM0436A86SQKA 8 Mb Synchronous Communication SRAM
Revision Log
Rev 8/26/99 9/16/99 Initial public release (00). Corrected VDD/V DDQ column in Ordering Information table. Release document version 01. Changed name of product to Synchronous Communication SRAM. Fixed notes on Cycle Definition Truth Table on page 6 Release document version 02. Updated ISB, IZZ , and ISB1 numbers. Updated TGLQV for -7 products. Updated ISb4 definition for Typo. Added Mechanical drawing. AC Test Conditions for 3.3V. Updated Active Currents. Updated description paragraph on page 1. Removed -8F sorts. Standardized Snooze mode to Sleep mode throughout. Removed Preliminary classification. Release document version 03. Contents of Modification
9/27/99
1/18/00
6/22/00 9/18/00 10/02/00 10/12/00
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a
Copyright and Disclaimer
Copyright International Business Machines Corporation 1999. All Rights Reserved Printed in the United States of America October 2000
The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both. IBM IBM logo PowerPCa
Other company, product and service names may be trademarks or service marks of others.
All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. The information contained in this document does not affect or change IBM's product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary.
THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document.
IBM Microelectronics Division 1580 Route 52, Bldg. 504 Hopewell Junction, NY 12533-6351
The IBM home page can be found at http://www.ibm.com The IBM Microelectronics Division home page can be found at http://www.chips.ibm.com
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